这篇博文开始讲ROM，在FPGA中的ROM可以同过加载文件的方式初始化ROM（就像定制IP核时加载coe文件），也可以通过case的方式在代码中进行初始化，这篇博文讲通过加载文件的方式初始化ROM，之后通过仿真读出来数据，看看是否成功。
Verilog描述：
`timescale 1ns / 1ps//// Create Date: /05/28 23:15:15// Design Name: // Module Name: rom_using_file//module rom_using_file (input [7:0] address , // Address inputoutput [7:0] data , // Data outputinput read_en , // Read Enable input ce // Chip Enable);reg [7:0] mem [0:255] ; assign data = (ce && read_en) ? mem[address] : 8'b0;initial begin$readmemb("G:/Verilog_file/Memory_/Memory_.srcs/sources_1/new/memory.list", mem); // memory_list is memory file// G:/Verilog_file/Memory_/Memory_.srcs/rom_using_file_sim/new/memory.list//G:/Verilog_file/Memory_/Memory_.srcs/sources_1/new/memory.listendendmodule
最文章的最后会粘出初始化文件memory.list.
通过在FPGA中测试，使用readmemb读出初始化数据时候，memory.list的路径要全，且分隔符是/而不是\。
下面给出测试文件：
`timescale 1ns / 1psmodule rom_using_file_tb;reg [7:0] address;reg read_en, ce;wire [7:0] data;integer i;initial beginaddress = 0;read_en = 0;ce= 0;//#10 $monitor ("address = %h, data = %h, read_en = %b, ce = %b", address, data, read_en, ce);for (i = 0; i < 256; i = i + 1 )begin#5 address = i;read_en = 1;ce = 1;#5read_en = 0;ce = 0;address = 0;endendrom_using_file U_rom(.address(address) , // Address input.data(data) , // Data output.read_en(read_en) , // Read Enable.ce(ce) // Chip Enable);endmodule
仿真结果：
从仿真波形图看，读出数据正常。
参考链接：ROM, EPROM, EEPROM
memory.list文件如下：
00000000000000010000001000000011000001000000010100000110000001110000100000001001000010100000101100001100000011010000111000001111000100000001000100010010000100110001010000010101000101100001011100011000000110010001101000011011000111000001110100011110000111110010000000100001001000100010001100100100001001010010011000100111001010000010100100101010001010110010110000101101001011100010111100110000001100010011001000110011001101000011010100110110001101110011100000111001001110100011101100111100001111010011111000111111010000000100000101000010010000110100010001000101010001100100011101001000010010010100101001001011010011000100110101001110010011110101000001010001010100100101001101010100010101010101011001010111010110000101100101011010010110110101110001011101010111100101111101100000011000010110001001100011011001000110010101100110011001110110100001101001011010100110101101101100011011010110111001101111011100000111000101110010011100110111010001110101011101100111011101111000011110010111101001111011011111000111110101111110011111111000000010000001100000101000001110000100100001011000011010000111100010001000100110001010100010111000110010001101100011101000111110010000100100011001001010010011100101001001010110010110100101111001100010011001100110101001101110011100100111011001111010011111101000001010000110100010101000111010010010100101101001101010011110101000101010011010101010101011101011001010110110101110101011111011000010110001101100101011001110110100101101011011011010110111101110001011100110111010101110111011110010111101101111101011111111000000110000011100001011000011110001001100010111000110110001111100100011001001110010101100101111001100110011011100111011001111110100001101000111010010110100111101010011010101110101101101011111011000110110011101101011011011110111001101110111011110110111111110000011100001111000101110001111100100111001011110011011100111111010001110100111101010111010111110110011101101111011101110111111110000111100011111001011110011111101001111010111110110111101111111100011111001111110101111101111111100111111011111111011111111
